1. Field of the Invention
The present invention generally relates to high bandwidth/performance Dynamic Random Access Memories (DRAMs) and, more particularly, to high bandwidth/performance DRAMs with improved command bus utilization for increased data input/output (I/O) capabilities.
2. Description of the Related Art
Dynamic random access memory (DRAM) performance is a well known limitation to computer system performance. Processor speeds are rapidly outpacing main memory performance, with both processor designers and system manufacturers developing higher performance memory subsystems in an effort to minimize performance limitations due to the slower DRAM devices. Ideally, the memory performance would match or exceed processor performance, i.e., a memory cycle time would be less than one processor clock cycle. This is almost never the case and, so, the memory is a system bottleneck. For example, a state of the art high speed microprocessor may be based on a 200 MegaHertz (MHZ) clock with a 5 nanosecond (ns) clock period. A high performance DRAM may have a 60 ns access time, which falls far short of processor performance.
This system bottleneck is exacerbated by the rise in popularity of multimedia applications. Multimedia applications demand several times more bandwidth for main memory or frame-buffer memory than computational intensive tasks such as spread sheet analysis programs or, other input/output (I/O) intensive applications such as word processing or printing.
Extended Data Out (EDO) and Synchronous DRAMs (SDRAMs) were developed to improve bandwidth. However, SDRAMs and EDO RAMs still do not match processor performance and, therefore, still limit system performance. Consequently, as faster microprocessors are developed for multimedia processing and high performance systems, faster memory architecture is being developed to bridge the memory/processor performance gap, e.g., wide I/O DRAMs.
Recent developments predict a major turning point for memory devices and related subsystems with a shift to high speed/narrow I/O devices. Recent developments in high bandwidth memory I/O design have shown performance advantages by separating memory command inputs from data I/O. This re-allocation of pin definition has increased the required memory function pins, but it has also permitted continuous data flow for high bandwidth memory. However, this re-allocation has also created a bus utilization inefficiency between command ports and data ports. While the data ports are continuously flipping direction to satisfy reading or writing of data, the command ports become active only when a new command packet must be received. This creates a bus efficiency imbalance which can impede performance and data rate potentials.